The present invention is related to systems and methods for performing data conversions, and more particularly to systems and methods for performing analog-to-digital conversions.
A variety of applications require signal conversion from the digital domain to the analog domain. For example, video is typically captured using an array of pixels, and analog values from those pixels are converted to the digital domain for further manipulation. Currently, pipelined analog-to-digital converters offer the most popular architectures for medium to high speed conversions. As one advantage, pipelined architectures can provide high throughput rates, and yet occupy a relatively small die area when compared to comparable non-pipelined architectures.
Because of non-idealities of components used to create analog-to-digital converters, redundancy is introduced into designs by making the sum of individual pipeline stages greater than the total resolution of the analog-to-digital converter. Redundancy may be introduced to any stage of a pipelined design. As just some examples, the redundancy may be introduced at the stage where the error is created by, for example, implementing a higher resolution analog-to-digital converter stage than that theoretically required. Alternatively, redundancy may be added in a subsequent stage that includes an operational range that is larger than is theoretically necessary. In a typical application, the number of comparators for a higher resolution stage is [2(B+1)−1] comparators, where B is the effective number of bits of the stage with redundancy. As an improvement, one reported design approach (hereinafter the “Lewis Approach”) allows for the reduction of one comparator such that [2(B+1)−2] comparators are used. This design is discussed in “A 10-b 20-Msamples/s Analog-to-Digital Converter,” Lewis et al., Journal of Solid State Circuits, Vol. 27, No. 3, March 1992.
Using the Lewis Approach, an analog-to-digital converter with two effective bits requires six comparators, three effective bits requires fourteen comparators, and four effective bits requires thirty comparators. From this, it can be appreciated that designing an analog-to-digital converter with a large number of effective bits will require a very large number of comparators. A large number of comparators requires substantial die area and consumes an appreciable amount of power.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for analog-to-digital conversion.